SCMOS Layout Rules - Poly2 (or Electrode) for Capacitor

The poly2 or electrode layer is a second polysilicon layer (physically above the standard, or first, poly layer). The oxide between the two polys is the capacitor dielectric. The capacitor area is the area of coincident poly and electrode.

Rule	Description	Lambda
11.1	Minimum width	3 [SUBM 4]
11.2	Minimum spacing	3
11.3	Minimum poly overlap	2 [SUBM 5]
11.4	Minimum spacing to active or well edge (not illustrated)	2
11.5	Minimum spacing to poly contact	3 [SUBM 6]

 

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SCMOS Layout Rules - Electrode for Transistor

Same electrode (second poly) layer as for caps

Rule	Description	Lambda
12.1	Minimum width	2
12.2	Minimum spacing	3
12.3	Minimum electrode gate overlap of active	2
12.4	Minimum spacing to active	1
12.5	Minimum spacing or overlap of poly	2
12.6	Minimum spacing to poly or active contact	3

Table 19: SCMOS Layout Rules - Electrode for Transistor (Analog Option)  

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SCMOS Layout Rules - Electrode Contact

The electrode is contacted through the standard contact layer, similar to the first poly. The overlap numbers are larger, however.

Rule	Description	Lambda
13.1	Exact contact size	2 x 2
13.2	Minimum contact spacing	2 [SUBM 3]
13.3	Minimum electrode overlap (on capacitor)	3
13.4	Minimum electrode overlap (not on capacitor)	2
13.5	Minimum spacing to poly or active	3

Table 20: SCMOS Layout Rules - Electrode Contact (Analog Option)